Doping of semiconductor substrates to form semiconductor devices is a well known practice in the art. To form memory devices, not only are the underlying substrate and source and drain regions implanted with dopant, but most often the conductive elements of the transistor gates are doped as well. In modern DRAM processing, typical and almost universal doping patterns for transistors in the prior art include utilizing a N+ doped polysilicon (poly) for the access transistor gates, N+ doped poly for periphery NMOS transistor gates, and N+ doped poly for periphery PMOS transistor gates. A new trend in the industry is to utilize a P+ doped poly for the periphery PMOS transistor gates.
In semiconductor device manufacture, a known problem is that as gate lengths of transistors are scaled to shorter and shorter lengths and gate dielectrics are reduced, the doping levels of the underlying channel region of the substrate must be increased to maintain sufficient access device threshold voltages (Vt). Current leakage is a problem with modern memory devices associated with such doping. There are two components to leakage: (1) transistor leakage, which may be reduced by increasing the substrate doping in the channel region, and thus increasing the Vt; and (2) diode leakage of the source/drain junction. A major problem is that efforts to alleviate one leakage problem worsens the other. For example, while increasing the channel region substrate doping raises Vt and reduces the transistor leakage problem, it worsens the diode leakage. Hence, when access devices are manufactured by current processes, they must be designed to balance theses two leakage components, which is becoming increasingly more difficult to do. Another problem is that as the array (channel region) doping levels increase in a DRAM array to set sufficient threshold voltage for the access transistor, DRAM refresh characteristics suffer.
To scale the DRAM die size smaller, the transistor gate lengths in both the array and periphery must be reduced. To support the shorter gate lengths and to minimize the power dissipation of increasing DRAM density, the operation voltage is reduced. The lower operating voltage and the reduction in gate length dictate that the gate dielectric is reduced to maintain sufficient switching performance. For NMOS transistors with N+ poly gate electrodes, as the gate oxide is reduced it is required to increase the channel doping to maintain a sufficiently high access threshold voltage.
In DRAM technology, a stored “one” will gradually become a “zero” as electrons refill the empty well. This phenomenon is the leakage described above. The nature of the one transistor DRAM cell is that “ones” gradually become “zeros” and “zeros” remain so. This phenomenon requires that the memory cell be refreshed periodically to maintain the correct data storage at each bit location. The total leakage current of the cell must be low enough that the cell does not discharge and lose its memory state. If a transistor could be designed to have less leakage current, the refresh characteristics of the DRAM would be improved.
It would be useful in DRAM device manufacturing to utilize a method of tailoring transistor threshold voltages specifically for the various transistors that required less channel dopant. It would be preferable if this tailoring of Vt could be accomplished while reducing the memory array substrate channel doping levels so as to minimize current leakage and improve refresh characteristics. Additionally, use of novel materials, that could be readily incorporated into standard DRAM processing, for transistor gate electrodes to accomplish the above would be advantageous.